1. Field of the Invention
The present invention relates to a time measurement device for measuring a time signal or a periodic signal output from, for example, a sensor of a process device such as a differential pressure detecting device.
2. Description of the Related Art
FIG. 1 shows an example of a conventional time measurement device, while FIG. 2 shows the waveforms of signals propagating from the device.
As shown in FIG. 1, this conventional time measurement device comprises counters C1 and C2, flip-flop circuits FF1 and FF2, and AND gates G1 and G2. CLK, CLR bar, and PIN respectively indicate a reference clock signal, a clear signal and a measurement input pulse.
Referring to FIGS. 1 and 2, the operations performed by this conventional time measurement device are described below.
As shown in (b) in FIG. 2, the clear signal CLR bar (CLR (-): a signal name attached with a bar indicates a signal which is significant at a low level ("L")) is first set to the low level, so that each element is reset. When the measurement input pulse PIN is input to the counter C1, as shown in (c) in FIG. 2, the counter C1 starts counting the pulses of the measurement input pulse PIN.
When the counter C1 counts eight pulses of the measurement input pulse PIN, an output GA bar (GA(-)) of the flip-flop circuit FF1 goes to "L", as shown in (d) in FIG. 2. Since an output GB bar (GB(-)) of the flip-flop circuit FF2 is "L" as shown (e) in FIG. 2 at this time, the AND gate G1 opens and its output signal GATE goes to a high level ("H"), as shown in (f) in FIG. 2. Next, when the counter C1 counts eight bits (2.sup.7 =128), the GB(-) goes to "H", as shown in (e) in FIG. 2. As a result, the signal GATE goes to "L". While the AND gate G1 is open, that is, while the signal GATE remains "H", the reference clock signal CLK shown in (a) in FIG. 2, passes through the AND gate G2 as a CLKG signal, as shown in (g) in FIG. 2. The counter C2 counts the pulses of the CLKG signal, so that the time value according to the cycle of the measurement input pulse PIN can be obtained.
Because the reference clock signal CLK is asynchronous with the rising or falling of the signal GATE (an asynchronous type), the four typical cases shown as the cases (1) through (4) of FIG. 3 may occur.
In these four cases, each of the count values is "5", and the gate width of the signal GATE is a multiple of 4.5 to 5.5 times the width (pulse cycle) of the reference clock signal CLK in case (1), a multiple of 4 to 5 in cases (2) and (3), and a multiple of 3.5 to 4.5 in case (4). That is, the gate width of this signal has a width of (4.5.+-.1).times.(pulse cycle of CLK). Since each of the count values does not vary if the gate width of the signal GATE varies in the range of (4.5.+-.1).times.(pulse cycle of CLK), an error of .+-.1 clock pulse occurs in a time measurement result. Consequently, the resolution of measurement deteriorates. Although a method for increasing the speed of the clock signal, or a method for extending the gate time (increasing the number of bits of the counter) may be considered in this case, the former has the problem that the electric current to be consumed becomes higher, while the latter has the problem that the measurement time becomes longer.
Therefore, the present applicant proposed the time measurement circuit shown in FIG. 4 in the Japanese Laid-Open Patent Publication TOKKAI-HEI 7-72273.
As is evident in comparison with the circuit shown in FIG. 1, this time measurement circuit is characterized in that flip-flop circuits FF3 and FF4 are added to the circuit shown in FIG. 1. INV shown in this figure indicates an inverter or inversion circuit. The flip-flop circuit FF3 holds the state of the clock signal CLK when the gate signal GATE rises (L.fwdarw.H), while the flip-flop circuit FF4 holds the state of the clock signal when the gate signal falls (H.fwdarw.L). These states are respectively represented by outputs BOA and BOB.
Provided below is an explanation about the operations performed by the time measurement circuit shown in FIG. 4, by referring to FIGS. 5 through 7.
FIG. 5 corresponds to FIG. 3, and represents the relationship between each of the CLK, GATE, CLKG signals, and the outputs BOA and BOB of FF3 and FF4.
In this figure, case (1) represents the case where both the outputs BOA and BOB become "1"; case (2) represents the case where BOA and BOB respectively become "1" and "0"; case (3) represents the case where BOA and BOB respectively become "0" and "1"; and case (4) represents the case where both BOA and BOB become "0". This time measurement circuit makes corrections, shown in FIG. 6, depending on the respective cases, so that a measurement error is within a range of .+-.0.5 clock pulse.
With this time measurement circuit, however, the two cases shown in (a) and (b) in FIG. 7 can be considered as the case where the leading (rising) or trailing (falling) edge of the gate signal GATE is almost the same timing as that of the rising or falling edge of the clock signal CLK. The case shown in (a) in FIG. 7 is the case where both the levels of the clock signal CLK at the leading and trailing edges of the gate signal GATE are determined to be "H", although the counter does not perform its count operations at times T1 and T2 (count value=5). In the meantime, the case shown in (b) in FIG. 7 is the case where the levels of the clock signal CLK at the leading and trailing edges of the gate signal are determined to be "L" although the counter performs its count operations at the times T1 and T2 (count value=7). The result of correction at this time will become (5.5.+-.1.5).times.CLK, whose error is larger than that in the result (6.+-.1).times.CLK in the case where the correction is not made.